This application claims the benefit of Japanese Patent Application No. 2001-170377 filed on Jun. 6, 2001, the contents of which are incorporated by reference.
The present invention relates to inter-processor communication systems and inter-processor communication methods used therefor and, more particularly, to an inter-processor communication method for a plurality of processors connected to a network, in which logical addresses are used as data read and write addresses.
In prior art inter-processor communication, the use of an erroneous data write address in a destination processor may causes system down condition in the destination processor. Accordingly, destination processor protection is provided by various means.
As an example, a received data buffer area is determined to permit writing of data only in this area in the inter-process communication (this method is hereinafter referred to as the first prior art technique). In this case, the receiver in the destination processor limits a write address to a physical address determined by the receiver, or to a region which is obtained by masking a physical address designated by the source processor with a mask bit pattern determined by the receiver.
As a different example, the source processor designates the write address not as a physical address but as a logical address (this method is hereinafter referred to as the second prior art technique). In this case, the receiver in the destination processor executes the translation of the write address from a logical address to a physical address. In this method, the physical address obtained by address translation in the receiver can be limited to be in a particular address range, and it is thus possible to protect the destination processor. However, if the designated write address is invalid, it would result in failure of the address translation.
In the above first prior art technique, because copying of data from the received data buffer area to a user's area is necessary, it causes degraded throughput performance and latency performance of the inter-processor communication. Accordingly, the second prior art technique method is frequently used, in which the write address is designated as a logical address.
In the second prior art technique, however, a means for translating the designated logical address to a physical address is necessary. This address translation is needed for each page, and the normal page size is 4 Kbytes. Therefore, transmission of a large quantity of data in the inter-processor communication requires a very large address translation table, which cannot be fully held in the receiver. Accordingly, the full address translation table is mounted in the main memory, and the receiver reads part of the table from the main memory as desired for the address translation.
This means that the address translation gives rise to access to the main memory, thus leading to overhead in the inter-processor communication. Particularly, when the main memory is accessed for address translation at the time of packet reception, the writing of packet data can be executed only after the address translation. Until the end of the address translation, therefore, the receiver cannot read data from the network. This has bad effects on other inter-processor communication as well. For improving the inter-processor communication performance, it is thus necessary to reduce such overhead.
The above prior art inter-processor communication has a problem that when the write address in the destination processor is designated as logical address in the parallel computer system, it is difficult to reduce or conceal the overhead in the address translation in the receiver.